Computer systems typically utilize a bus system. Several devices are typically coupled to a data bus. Some prior bus systems operate synchronously, i.e., using a clock signal to validate data signals. Within synchronous bus systems, clock-data skew can be a concern because such skew can prevent the clocking of valid data. Thus, data errors can result from clock-data skew. Clock-data skew results from the difference between data signal propagation delay and clock signal propagation delay.
For certain prior art synchronous bus systems with sufficiently short bus and clockline lengths, clock-data skew might not be a concern because clock and data signals have only a short distance to travel and arrive nearly instantaneously. Within a synchronous bus system with a long data bus and a long clockline, clock-data skew is often a concern, however, especially if high clock speeds are desired. Within many prior art synchronous bus systems, a clock period must exceed clock signal propagation delay. Put another way, clock speed must generally slow as clockline length increases. This prior art relationship is expressed by Expression 1:
(1) Clock Period&gt;set-up time of data to clock signal+hold time of data to clock signal+clock-data skew
One prior art scheme for reducing clock-data skew error is illustrated in FIG. 1. Rather than using a single clock source, multiple clock sources are used. That is, many matched clock lines are coupled to a single clock generator. The clock lines are matched so that a clock signal arrives at each device at substantially the same point in time, despite long clockline lengths. Thus, the bus system shown must operate with a clock period that is greater than or equal to the data propagation delay of the bus plus clock data skew plus clock to data hold time plus clock to data set-up time.
One disadvantage of the bus system of FIG. 1, however, is the relative complexity of that bus system. A clockline is required for each device that is clocked and each clockline typically must be carefully tuned to ensure simultaneous clocking of all devices. Another disadvantage of the bus system of FIG. 1 is that its clock period is limited by the propagation delay of the data bus.
FIG. 2 illustrates a different prior art synchronous bus system scheme utilizing a long data bus. The master device generates two clock signals--namely, a receive clock, RCLK, and a transmit clock, TCLK. In conjunction with appropriate frame control signals, the receive clock is used to clock both the transmission of data by slave devices and the reception of data by the master device. The bus system of FIG. 2 thus decouples clock period from the propagation delay of the data bus.
A disadvantage of the bus system scheme of FIG. 2 is that two clock sources are required (rather than a single clock source) in addition to control signals. A further disadvantage is that the bus system of FIG. 2 permits only one master device.